Foundry Integration of Carbon Nanotube FETs With 320 nm Contacted Gate Pitch Using New Lift-Off-Free Process
Andrew Yu, Tathagata Srimani, C.L. Lau, Brian Benton, Mark Nelson, Max M. Shulaker
Abstract
While advances with silicon-based technologies continue to be made, alternative technologies to supplement Silicon are currently being explored. Carbon nanotube (CNT) field-effect transistors (CNFETs) are a leading proposed candidate for back-end-of-line (BEOL) heterogenous integration with silicon. However, a challenge facing the scalability and performance of heterogeneously integrated CNTs and other nanomaterials is the current use of non-standard metal evaporation and lift-off for contact metallization. We experimentally demonstrate a new VLSI-compatible, lift-off-free CNFET process that uses conventional sputtered liner and tungsten metal fill/damascene for contact formation. This process is implemented in a commercial silicon CMOS foundry and demonstrates improved scalability and performance (~ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2\times $ </tex-math></inline-formula> higher on-current and ~40% lower subthreshold swing) compared to lift-off processing. All processing is low-temperature (≤415°C) and thus still (BEOL) compatible.