A Physical Model for Bulk Gate Insulator Trap Generation During Bias-Temperature Stress in Differently Processed p-Channel FETs

Tarun Samadder, Nilotpal Choudhury, Satyam Kumar, Dimple Vijay Kochar, Narendra Parihar, Souvik Mahapatra

2021IEEE Transactions on Electron Devices23 citationsDOI

Abstract

A deterministic reaction-diffusion–drift model is used for the time kinetics of bulk gate insulator trap generation in p-channel Field Effect Transistors (FETs) under inversion stress. The consistency of the deterministic and stochastic versions of the model is shown. The model is independently validated using stress-induced leakage current data from various reports. The model is incorporated into the already existing bias temperature instability (BTI) analysis tool framework and validated using negative BTI data. The measured data from FinFETs having different channel material, substrate type, gate insulator process, and fin length, as well as gate-all-around stacked nano sheet (GAA-SNS) FETs are modeled.

Topics & Concepts

Materials scienceOptoelectronicsSilicon on insulatorElectronic engineeringTransistorField-effect transistorLogic gateNegative-bias temperature instabilityStress (linguistics)Insulator (electricity)MOSFETElectrical engineeringEngineeringSiliconVoltagePhilosophyLinguisticsSemiconductor materials and devicesAdvancements in Semiconductor Devices and Circuit DesignFerroelectric and Negative Capacitance Devices