3D Monolithically Integrated Device of Si CMOS Logic, IGZO DRAM-like, and 2D MoS<sub>2</sub> Phototransistor for Smart Image Sensing
F.M. Lee, Po-Hao Tseng, Yi‐Ting Lin, Yu‐Hsuan Lin, Wen-Lu Weng, N.-C. Lin, P.-J. Sung, Chih-Chyau Yang, Wen-Fa Wu, Chen Shen, Po-Hsun Chen, Y. H. Lee, M. H. Lee, K. C. Wang, C.-Y. Lu
Abstract
We proposed a three-tier monolithic 3D (M3D) integration technology and constructed a unique platform to enable smart image sensor on an 8" Si wafer. In this platform, the 1 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">st</sup> tier’s laser-annealed 20nm Si FinFETs successfully demonstrated logic inverter, NAND and NOR functions. The 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> tier’s IGZO DRAM-like devices provided long data retention (>1000s) and robust non-destructive high current read. It is capable to serve as low-power working memory and MAC accelerator for computing-in-memory functions when configured in AND-type array. The top layer is a 5x5 array of MoS <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> TMD phototransistors with ultrahigh responsivity (>10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> A/W) and tunable photogain (10°~10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> ) for image sensing. All the functional units were fabricated by low-thermal budget processes and were connected by fine- pitch vertical interconnects for parallel signal processing.