Ultrahigh PSR Output-Capacitor-Free Adaptively Biased 2-Power-Transistor LDO With 200-mV Dropout
Xu Han, Wing‐Hung Ki, Lianbo Wu, Yuan Gao
Abstract
This letter presents an output-capacitor-free cascaded 2-power-transistor low-dropout (2-PT LDO) regulator with ultrahigh power supply rejection (PSR) and fast transient response for low-power biomedical system on chips. The proposed 2-PT LDO consists of two stages in series, and the total dropout voltage is 200 mV. In order to boost the total PSR in a wide frequency range, different PSR enhancement strategies are adopted in each stage and a reversed-phase supply-ripple-cancelation technique is provided by a proposed reference buffer to further improve the PSR performance. Furthermore, adaptive biasing with robust frequency compensation is utilized to maintain system stability with fast transient response. Designed and fabricated in a 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS process, the active area is only 0.0237 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . With the input voltage of 1.1–1.2 V, the 2-PT LDO supplies 0.9–1 V with a total quiescent current of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$24.2~\mu \text{A}$ </tex-math></inline-formula> at no-load current. Experimental results show that PSR is better than −95dB up to 100 kHz.