Design and Performance Evaluation of Energy Efficient 8-Bit ALU at Ultra-Low Supply Voltages Using FinFET with 20 nm Technology
Vallabhuni Vijay, Pittala Chandra Shekar, Shaik Sadulla, Putta Manoja, Rallabhandy Abhinaya, Merugu Rachana, Nakka Nikhil
Abstract
In the last few years, the tiny size of MOSFET (i.e., less than tens of nano-meters) created some operational problems such as increased gate-oxide leakage, amplified junction leakage, high sub-threshold conduction, and reduced output resistance. To overcome the above challenges, FinFET has the advantages of an increase in the operating speed, reduced power consumption, decreased static leakage current is used to realize the majority of the applications by replacing MOSFET. By considering the attractive features of the FinFET, an ALU is designed as an application. In the digital processor, the arithmetic and logical operations are executed using the arithmetic logic unit (ALU). In this chapter, power-efficient 8-bit ALU is 68designed with full adder (FA) and multiplexers composed of gate diffusion input (GDI) which gained the designer’s choice for digital combinational circuit realization at minimum power consumption. The design is simulated using Cadence virtuoso with 20 nm technology. Comparative performance analysis is carried out in contrast to the other standard circuits by taking the critical performance metrics such as delay, power, and power delay product (PDP), energy-delay product (EDP) metrics into consideration.