Modelling for triple gate spin‐FET and design of triple gate spin‐FET‐based binary adder
Gul Faroz A. Malik, Mubashir A. Kharadi, Nusrat Parveen, Farooq Ahmad Khanday
Abstract
In this study, an InAs channel‐based triple gate spin‐field effect transistor (FET) model is proposed. The proposed triple‐gate spin‐FET offers a high density of integration, consumes low power and offers very high switching speed. By incorporating the suitable parameters like channel length, spin diffusion length, channel resistance and junction polarisation, the modelled triple gate spin‐FET is then used to implement 3‐input XOR, 3‐input XNOR and majority gate functions. The designs of 3‐input XOR and majority gates were achieved keeping in view that the sum operation of a 1‐bit full adder is obtained through XOR gate and the carry operation of 1‐bit full adder is obtained through majority gate. Therefore, for designing a 1‐bit full adder, only two spin‐FETs will be required which signifies the compact nature of the design. In addition, a 2‐bit ripple adder is designed with cascading two 1‐bit full‐adders. Finally, a comparative analysis of the proposed gates and 1‐bit full adder with the reported work and conventional CMOS design was carried out in terms of employed number of devices, power consumption and speed. The analysis shows that proposed gates/adder offer better performance than the reported work and conventional CMOS designs.