First Demonstration of Dual-Gate IGZO 2T0C DRAM with Novel Read Operation, One Bit Line in Single Cell, I<sub>ON</sub>=1500 μA/μm@V<sub>DS</sub>=1V and Retention Time>300s
Wendong Lu, Zhengyong Zhu, Kaifei Chen, Menggan Liu, Bok-Moon Kang, Xinlv Duan, Jiebin Niu, Fuxi Liao, Dan Wang, Xie-Shuai Wu, Joohwan Son, Deyuan Xiao, Guilei Wang, Abraham Yoo, Kan-Yu Cao, Di Geng, Nianduan Lu, Guanhua Yang, Chao Zhao, Ling Li, Ming Liu
Abstract
For the first time, we propose and experimentally demonstrate one novel dual-gate (DG) IGZO 2T0C cell design for high-density and high-performance DRAM application. Through process optimization, ultra-scaled DG IGZO transistor of $\mathrm{L}_{\mathrm{C}\mathrm{H}}=13.9$nm achieves ultra-high on-state current of 1500$\mu$A/$\mu$ m@$\mathrm{V}_{\mathrm{D}\mathrm{S}}=1$V and low $\mathrm{R}_{\mathrm{C}}$. By using one gate of DG IGZO FET to control read operation and another gate to store data in 2T0C configuration, this new 2T0C cell provides more reliable gate-controlled read scheme. Basic write and read operation with data “1” (1V) and “0” (OV) are successfully exhibited with retention time longer than 300s. Furthermore, only one bit line in each cell is used in our new proposed DG scheme, which could help reduce the critical dimension for bit-line (BL) sense amplifier circuit. This work paves the forward way for high density IGZO 2T0C DRAM application.