Customized Posit Adders and Multipliers using the FloPoCo Core Generator
Raúl Murillo, Alberto A. Del Barrio, Guillermo Botella
Abstract
The posit number system, which is proposed as a replacement of IEEE floating-point numbers, is in the spotlight of Arithmetic research due to the recent breakthroughs. This format claims to provide more accurate results with the same bitwidth than standard floating point, but the run-time variability during the detection of the posit fields involves a hardware design challenge. In this work, we propose parameterized designs for multiple posit functional units, including addition and multiplication, and integrate them as templates of the FloPoCo framework. The integration of the proposed algorithms within FloPoCo can provide synthesizable VHDL code for posit arithmetic of any possible configuration 〈n, es〉. Experiments show an improvement in terms of area and energy with respect to state-of-the-art works up to 35.9% and 30.8%, respectively.