Hybrid Lockstep Technique for Soft Error Mitigation
M. Peña-Fernández, Alejandro Serrano-Cases, Almudena Lindoso, Sergio Cuenca-Asensi, Luis Entrena, Yolanda Morilla, Pedro Martín‐Holgado, Antonio Martínez-Álvarez
Abstract
This work presents the evaluation of a new dual-core lockstep hybrid approach aimed to improve the fault tolerance in microprocessors. Our approach takes advantage of modern multicore processor resources to combine software-based lockstep with a custom hardware observer. The first is used to duplicate data and instruction flows; meanwhile, the second is in charge of the control-flow monitoring. The proposal has been implemented in a dual-core ARM microprocessor and validated with low-energy proton irradiation and emulated fault injection campaigns. The results show an improvement of one order of magnitude in the cross section of the benchmarks tested, even considering the worst case scenario.