Design of CNTFET-Based Ternary ALU Using 2:1 Multiplexer Based Approach
Sharvani Gadgil, Chetan Vudadha
Abstract
In view of the problems arising due to the scaling of the silicon transistor, different post-silicon, post-binary logic technologies are being explored by researchers. Implementation of Ternary Logic Circuits using Carbon Nanotube Field Effect Transistors (CNTFETs) is one such alternative. CNTFETs are an ideal choice for implementing ternary logic circuits since using CNTFETs multiple threshold voltages can be obtained by changing their physical dimensions. This paper presents a new design for a 2-digit Ternary Arithmetic and Logic Unit (TALU) using CNTFETs. The proposed TALU architecture consists of a function select block, a transmission gate block, and functional modules. In this design, the functional modules are implemented using a 2:1 multiplexer based design approach. This eliminates the need for decoders at the input resulting in lesser number of transistors when compared to existing designs. The proposed 2:1 multiplexer based approach results in lower power consumption in proposed Adder-subtractor and Multiplier modules as compared to existing ones. HSPICE based circuit simulations were performed on the proposed and existing TALU designs. Simulation results show an improvement of up to 96% in power and up to 95% in PDP for the Adder-subtractor and Multiplier modules. An improvement of up to 90% in power and up to 93% in PDP is obtained for the proposed TALU design as compared to the designs existing in the literature.