Performance and communication energy constrained embedded benchmark for fault tolerant core mapping onto NoC architectures
Aruru Sai Kumar, T. Venkatappa Rao, B. Naresh Kumar Reddy
Abstract
Due to the rapid growth of the components encapsulated on the on-chip architecture, the performance degradation and communication issues between the cores significantly impact NoC architecture. It also increases the possibility of core failures encountered in an application, leading to a faulty network. This research implemented fault-tolerant mapping algorithm (FTMAP) that focuses predominantly on replacing the faulty cores and assessing the communication and the execution time of the network by employing it on various multimedia benchmarks. The experimental outcomes reveal that it reduces the communication energy by 8%, 12%, 14% with respect to NFT, 1FT, 2FT compared to FTTG and 6%, 9%, 10% with respect to NFT, 1FT, 2FT when compared to K-FTTG. The reduction of the execution time has also outperformed by 18%, 24%, 26% with respect to NFT, 1FT, 2FT compared to FTTG and 13%, 19%, 21% with respect to NFT, 1FT, 2FT when compared to K-FTTG.