A 0.4-V 8400-μm<sup>2</sup> Voltage Reference in 65-nm CMOS Exploiting Well-Proximity Effect
Chengyu Che, Ka‐Meng Lei, Rui P. Martins, Pui‐In Mak
Abstract
This brief exploits, for the first time, the well-proximity effect to develop a sub-0.5 V voltage reference with a high power-supply rejection ratio (PSRR) and a compact area. The layout-dependent effect (LDE) is deemed to affect the matching and characteristics of analog circuits in the deep-submicron CMOS process. Here we explore the LDE effect in designing analog circuits, by exemplifying it with a CMOS voltage reference. Validated in 65-nm CMOS, the voltage reference occupies 8, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$400~\mu $ </tex-math></inline-formula> m2 and outputs a reference of 107.2 mV at a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}_{\mathrm{ DD}}$ </tex-math></inline-formula> of 0.4 V, with a power of 56.7 nW. The temperature coefficient is 79.4 ppm/°C across −20 to 80 °C (average of 12 samples) after a two-point batch trimming and scores a high PSRR of −66.5 dB. The standard deviation of 12 chips is 2.6 mV, evincing the robustness of the voltage reference exploiting the LDE.