Robust Recovery Scheme for MFIS-FeFETs at Optimal Timing with Prolonged Endurance: Fast-Unipolar Pulsing (100 ns), Nearly Zero Memory Window Loss (0.02 %), and Self-Tracking Circuit Design
Cheng‐Hsien Wu, Jingyu Liu, Xiaoting Zheng, Yi-Ming Tseng, Masaya Kobayashi, Vita Pi‐Ho Hu, C.-J. Su
Abstract
This work systematically demonstrates a novel recovery scheme for MFIS-FeFET memory arrays involving device fabrication and circuit integration. For the first time, the timing to initiate recovery to prolong the endurance of FeFETs is studied. A 100-ns fast-unipolar pulsing (FUP) recovery treatment at optimized timing is demonstrated with significantly extending endurance cycles by a factor of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , together with a nearly zero loss (0.02 %) in memory window (MW) per recovery period and a low MW fluctuation. An ultra-low recovery-induced time loss ratio of 5×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-5</sup> % is achieved. Based on the developed scheme, we propose a self-tracking recovery circuit design utilizing current-mode memory sensing to monitor the degree of fatigue and automatically trigger the recovery operation.