2T1C DRAM based on semiconducting MoS<sub>2</sub> and semimetallic graphene for in-memory computing
Saifei Gou, Yin Wang, Xiangqi Dong, Zihan Xu, Xinyu Wang, Qicheng Sun, Yufeng Xie, Peng Zhou, Wenzhong Bao
Abstract
In-memory computing is an alternative method to effectively accelerate the massive data-computing tasks of artificial intelligence (AI) and break the memory wall. In this work, we propose a two-transistor-one-capacitor (2T1C) DRAM structure for in-memory computing. It integrates a monolayer graphene transistor, a monolayer MoS<sub>2</sub> transistor, and a capacitor in a 2T1C configuration. In this structure, the storage node is similar to that of 1T1C dynamic random-access memory (DRAM), while an additional graphene transistor is used to accomplish the non-destructive readout of the stored information. Furthermore, the ultralow leakage current of the MoS<sub>2</sub> transistor enables the storage of multi-level voltages with a long retention time. The stored charges can effectually tune the channel conductance of the graphene transistor due to its excellent linearity so that analog multiplication can be realized. Our 2T1C DRAM exhibites potential for <i>in situ</i> training and recognition that can improve the recognition accuracy of neural networks.