A 1Tb 3b/Cell 8th-Generation 3D-NAND Flash Memory with 164MB/s Write Throughput and a 2.4Gb/s Interface
Moosung Kim, Sung Won Yun, Jungjune Park, Hyun Kook Park, Jungyu Lee, Yeong Seon Kim, Daehoon Na, Sara Choi, Youngsun Song, Jonghoon Lee, Hyun-Jun Yoon, Kangbin Lee, Byunghoon Jeong, Sanglok Kim, Junhong Park, Cheon An Lee, Jaeyun Lee, Jisang Lee, Jin Chun, Joonsuc Jang, Younghwi Yang, Seung Hyun Moon, Myung-Hoon Choi, Wontae Kim, Jungsoo Kim, Seok-Min Yoon, Pansuk Kwak, Myunghun Lee, Raehyun Song, Sung‐Hoon Kim, Chi-Weon Yoon, Dongku Kang, Jin-Yub Lee, Jaihyuk Song
Abstract
As data sizes increase exponentially, the demand for higher-density NAND with a smaller cell size and a higher interface speed has also increased [1]–[4]. However, the increased number of WL-stack layers results in a smaller sensing circuit size and a smaller WL-to-WL spacing, which increases the intrinsic transistor variation and the inter-cell interference. One way to achieve good density while maintaining system performance is to support more multiple-plane operations with a circuit under cell array architecture, which leads to an increased noise power. Moreover, to achieve a 2.4Gb/s the I/O circuits need to support the faster speed while achieving lower power consumption. This paper presents the offset cancelling sensing latch (OCSL) scheme, the quad-group interference-free read (Q-IFR) scheme, and the common-source line (CSL) noise-tracking scheme to resolve the aforementioned challenges. In terms of the high-speed I/O bandwidth, a receiver circuit and an internal reference voltage generator are also proposed to increase the I/O speed, reduce the standby power consumption, and reduce the settling time when the chip is enabled.