Performance Improvement of Spacer-Engineered N-Type Tree Shaped NSFET Toward Advanced Technology Nodes
Ummadisetti Gowthami, Asisa Kumar Panigrahy, Shobha Rani Depuru, Muralidhar Nayak Bhukya, V. Bharath Sreenivasulu, M. Durga Prakash
Abstract
Tree-shaped Nanosheet FETS (NSFET) is the most dependable way to scale down the gate lengths deep. This paper investigates the 12nm gate length (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> ) n-type Tree-shaped NSFET with the gate having a stack of high- <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> dielectric (HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) and SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> using different spacer materials, which can be done using TCAD simulations. The Tree-shaped NFET device with T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">(NS)</sub> = 5 nm, W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">(NS)</sub> = 25 nm, W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IB</sub> = 5 nm, and H <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IB</sub> = 25 nm has high on-current ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I<sub>ON</sub></i> ) and low off-current ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I<sub>OFF</sub></i> ). The 3D device with single- <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> and dual- <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> spacers are compared and its DC characteristics are shown. It is noted that the dual- <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> device achieves the maximum <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I<sub>ON</sub></i> / <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I<sub>OFF</sub></i> ratio, which is 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">9</sup> , compared to 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> because the fringing fields with spacer dielectric lengthen the effective gate length. Additionally, the impact of work function, interbridge height, width, gate lengths, and temperature, along with the device’s analog/RF and DC metrics, is also investigated in this paper. Even at 12 nm L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> , the proposed device exhibits good electrical properties with DIBL = 23 mV/V and SS = 62 mV/dec and switching ratio ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I<sub>ON</sub></i> / <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I<sub>OFF</sub></i> ) = 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">9</sup> . The device’s performance confirms that Moore’s law holds even for lower technology nodes, allowing for further scalability.