E-Core Implementation in Intel 4 with PowerVia (Backside Power) Technology
M. Shamanna, Eli Abuayob, G. Aenuganti, Cláudia Álvares, Joseph Antony, A. Bahudhanam, Amal Chandran, Peng Siew Chew, Amitava Chatterjee, Bharti Chauhan, N. Dandeti, J. Desai, Michael J. Doyle, T. Dmukauskas, P. Farache, E. Fetzer, K. Fischer, P. Hack, Yuval Greenzweig, John A. Giacobbe, W. Hafez, Erik Haralson, Aditya Hegde, A. Illa, Mohammad Saiful Islam, Shailendra Jain, M. Jang, Jessica Nguyen, Tom Tong, Lei Jiang, Eric Karl, Pavankumar Kalangi, G.F.W. Khoo, A. Krishnamoorthy, Brian Kuns, Wei Li, Rick Livengood, T. Malik, R Priyanka, Hasan Mohammad Faraby, Y. Maymon, K. Mistry, Keith Morgan, S. Natarajan, O. Nevo, M. Oh, Patrick Pardy, Jang Hyeok Park, Padma Penmatsa, Brady M. Phelps, C. Peterson, S. RAJAPPA, Adi Raveh, Alireza R. Rezaie, T. Ravishankar, R. Ramaswamy, S.M. Reddy, Rajarshi Saha, Shreyas Sen, Ricardo M. Sánchez, R. Sanaga, B. Simkhovich, B. Sell, M. Senger, B. Schnarch, M. Seshadri, O. Sidorov, Srinivas Subramaniam, K. Subramanian, B.T. Truong, S. Bangalore, J. Hicks, S. Venkatesh, D. Christensen, K. Bhargav, Martin von Haartman, P. Joshi, Scot E. Zickel, C-H. Lin, Jennifer Huening, Tai-Chi Wu, Nathan Bakken, Anis Afzal, Arun Raman, Sj. Rao, V. Kawar, J. Neirynck, D. K. Bradley, M. Duwe, S. L. Wu, Venkanagouda. C Patil, M. Bayoumy
Abstract
PowerVia Technology [1] is a novel innovation to extend Moore’s Law scaling by having Power Delivery on the backside. This paper presents the pre & post-silicon findings from implementing an Intel E-Core in PowerVia Technology. PowerVia enabled standard cell utilization of >90% in large areas of the core while showing >5% Frequency benefit in Silicon due to reduced IR drop. Successful Post-Silicon debug is demonstrated with slightly higher but acceptable throughput times. The thermal characteristic of the PowerVia test-chip is in line with higher power densities expected from logic scaling.