Tunable Non-Volatile Gate-to-Source/Drain Capacitance of FeFET for Capacitive Synapse
Tae‐Hyeon Kim, Omkar Phadke, Yuan-Chun Luo, Halid Mulaosmanovic, Johannes Mueller, Stefan Duenkel, Sven Beyer, Asif Islam Khan, Suman Datta, Shimeng Yu
Abstract
Using “capacitive” crossbar arrays for compute-in-memory (CIM) offers higher energy efficiency compared to “resistive” crossbar arrays. The non-volatile capacitive (nvCap) synapse has been recently reported in MFM and MFS stacks with asymmetric electrode interfaces. In this work, a foundry FeFET is leveraged as the capacitive synapse for the first time, where the tunable gate-to-drain and gate-to-source capacitances ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${C}_{{\text {gd}}}$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${C}_{{\text {gs}}}$ </tex-math></inline-formula> ) are exploited as the capacitive memory states. High capacitance on/off ratio (~25) is obtained by relatively low program/erase voltages (±3.5V). Furthermore, it is demonstrated by TCAD simulation that the physical origins of on-state and off-state capacitance are dominated by the inversion capacitance and the overlap capacitance, respectively. Based on these results, design guidelines are presented to further increase the on/off ratio.