Advanced HDFO Packaging Solutions for Chiplets Integration in HPC Application
Lihong Cao Teck Lee, Yung-Shun Chang, SimonYL Huang, J. Salenc ̧on, Emmal Lin, Owen Ou Yang
Abstract
As the industry enters the digital transformation and exascale computing era, massive compute with high frequent access to data is required for high performance computing (HPC) applications. The increasing amount of data from all sectors is raising a problem of operational and storing cost of the data. Meanwhile, the exponential cost of silicon scaling has created an inflection point for the industry. Die partitioning and chiplets integration provides more flexible mix-and-match systems to accelerate performance and power efficiency. It is driving the development of advanced packaging technology to enable chiplets with separate designs and different manufacturing process nodes within a single package for yield improvement, IP reuse, performance and cost optimization, as well time to market reduction. In this paper, different advanced high density Fanout (HDFO) technologies have been developed for chiplets integration in HPC applications. Various FOCoS (FanOut Chip on Substrate) solutions e.g. FOCoS chip first (FOCoS-CF), FOCoS chip last (FOCoS-CL) and a Stacked Si bridge FOCoS (sFOCoS) will be introduced. Especially, sFOCoS chip last solution will be the 1 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">st</sup> time presented in this paper. Furthermore, the impact of molding materials and underfill selections on the warpage for multiple chiplets integration are also discussed. The results indicate that the compatibility among the multi-layer stacked materials (Si, Cu, PI, Molding compounds, Underfills) play critical roles in warpage control at wafer level, fanout module level and package level. Finally, the comparison on warpage and reliability validation for chiplets integration among different HDFO solutions have been elaborated.