Cryo-CMOS modeling and a 600 MHz cryogenic clock generator for quantum computing applications
Q. Xue, Yuanke Zhang, Mingjie Wen, Xiaohu Zhai, Yuefeng Chen, Tengteng Lu, Chao Luo, Guo‐Ping Guo
Abstract
The development of large-scale quantum computing has boosted an urgent desire for the advancement of cryogenic CMOS (cryo-CMOS), which is a promising scalable solution for the control and read-out interface of quantum bits. In this paper, 180 nm CMOS transistors are characterized and modeled down to 4 K, and the impact of low-temperature transistor performance variations on circuit design is also analyzed. Based on the proposed cryogenic model, we present a 180 nm CMOS-based 450-850 MHz clock generator operating at 4 K for quantum computing applications. At 600 MHz output frequency, it achieves <4.8 ps RMS jitter with 30 mW power consumption (with test buffer), corresponding to a -211.6 dB jitter-power FOM, which is suitable for providing a stable clock signal for the control and readout electronics of scalable quantum computers.