Design and Performance Optimization of Junctionless Bottom Spacer FinFET for Digital/Analog/RF Applications at Sub-5nm Technology Node
Sresta Valasa, K. V. Ramakrishna, Narendar Vadthiya, Sunitha Bhukya, N. Bheema Rao, Satish Maheshwaram
Abstract
This article for the first time reports the design and performance optimization of Junctionless (JL) Bottom spacer (BSP) FinFET. Initially to get the desired value of workfunction ( <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML" overflow="scroll"> <mml:msub> <mml:mrow> <mml:mi>∅</mml:mi> </mml:mrow> <mml:mrow> <mml:mi>m</mml:mi> </mml:mrow> </mml:msub> </mml:math> ) and fin thickness (T fin ) for analog/RF analysis, the optimization of these parameters has been done by considering several values. It has been noticed that the increase in <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML" overflow="scroll"> <mml:msub> <mml:mrow> <mml:mi>∅</mml:mi> </mml:mrow> <mml:mrow> <mml:mi>m</mml:mi> </mml:mrow> </mml:msub> </mml:math> and reduction in T fin can lead to better electrical performance with suppressed short channel effects (SCE). Further, it is also observed that reduction in bottom spacer height (H BSP ) can fetch enhanced analog/RF performance considering the improvement noticed in transconductance (g m ), intrinsic gain (A V ), transconductance generation factor (TGF), cutoff frequency (f T ), and Gain frequency product (GFP). Moreover, when the bottom spacer dielectric permittivity (K BSP ) is increased from 3.9 to 22, it has been found that the analog/RF performance degrades significantly.