Reduced switch count‐based <i>N</i> ‐level boost inverter topology for higher voltage gain
Marif Daula Siddique, B. Prathap Reddy, Atif Iqbal, Saad Mekhilef
Abstract
This study proposes a new boost inverter based on a switched‐capacitor concept with reduced switch count. The basic unit is a five‐level topology, which inherently generates the AC output voltage with the self‐voltage balancing of the capacitors. A conventional carrier‐based sinusoidal modulation technique has been designed to maintain the capacitor voltage up to the input source voltage. The N ‐level structure of the proposed basic unit is also presented, which has the additional advantage of higher voltage gain with a single input. A detailed comparison with other similar topologies has been carried out. A laboratory prototype has been used to test the workability of the proposed basic unit and its extension for seven‐level through several results.