Parallel Photonic Convolutional Processing on-Chip With Cross-Connect Architecture and Cyclic AWGs
Bin Shi, Nicola Calabretta, Ripalta Stabile
Abstract
Convolutional neural network (CNN) is one of the best neural network structures for solving classification problems. The convolutional processing of the network dominates processing time and computing power. Parallel computing for convolutional processing is essential to accelerate the computing speed of the neural network. In this paper, we introduce another domain of parallelism on top of the already demonstrated parallelisms suggested for photonic integrated processors with WDM approaches, to further accelerate the convolutional operation on chip. The operation of the novel parallelism is introduced with an updated cross-connect architecture, exploiting cyclic array waveguide grating. The photonic CNN system is demonstrated for the handwritten digit classification problem in simulation, with a speed of 2.56 Tera operation/s and end-to-end system energy efficiency of 3.75 pJ/operation, using 16 weighting elements and 10 Giga sample/s inputs. The proposed parallelism improves CNN acceleration by 4-16 times with respect to state-of-the-art integrated convolutional processors, depending on the available weighting elements per convolutional core.