Litcius/Paper detail

Impact of interface trap charges on electrical performance characteristics of a source pocket engineered Ge/Si heterojunction vertical TFET with HfO2/Al2O3 laterally stacked gate oxide

Manas Ranjan Tripathy, A Samad, Ashish Kumar Singh, Prince Kumar Singh, Kamalaksha Baral, Ashwini Kumar Mishra, Satyabrata Jit

2021Microelectronics Reliability47 citationsDOI

Topics & Concepts

Materials scienceTransconductanceOptoelectronicsHeterojunctionTransistorElectrical engineeringVoltageEngineeringAdvancements in Semiconductor Devices and Circuit DesignSemiconductor materials and devicesNanowire Synthesis and Applications