Progress Toward Superconductor Electronics Fabrication Process With Planarized NbN and NbN/Nb Layers
Sergey K. Tolpygo, Justin Mallek, Vladimir Bolkhovsky, Ravi Rastogi, Evan B. Golden, Terence J. Weir, L. M. Johnson, M.A. Gouker
Abstract
In order to increase circuit density of superconductor digital and neuromorphic circuits by 10× and reach integration scale of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sup> Josephson junctions (JJs) per chip, we developed a new fabrication process on 200-mm wafers, using self-shunted Nb/Al-AlO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> /Nb JJs and kinetic inductors for cell miniaturization. The process has one layer of JJs, one layer of resistors, and ten fully planarized superconducting layers: 8 niobium layers and two layers of high kinetic inductance materials, Mo <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> N and NbN, with sheet inductance of 8 pH/sq and 3 pH/sq, respectively. The minimum linewidth of NbN kinetic inductors is 250 nm. NbN films were deposited by two methods: with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">${T}_c \approx $</tex-math></inline-formula> 15.5 K by reactive sputtering of a Nb target in Ar+N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> mixture; with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">${T}_c$</tex-math></inline-formula> in the range from 9 K to 13 K by plasma-enhanced chemical vapor deposition (PECVD) using Tris(diethylamido)(tert-butylimido)niobium(V) metalorganic precursor. PECVD of NbN was investigated to obtain conformal deposition and filling narrow trenches and vias with high depth-to-width ratios, <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d/w</i> >1, which was not possible to achieve using sputtering and other physical vapor deposition methods at temperatures below 200 °C required to prevent degradation of Nb/Al-AlO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> /Nb junctions. Nb layers with 200 nm thickness are used in the process layer stack as ground planes to maintain a high level of interlayer shielding and low intralayer mutual coupling, for passive transmission lines with wave impedances matching impedances of JJs, typically ≤50 Ω, and for low-value inductors. NbN and NbN/Nb bilayer are used for cell inductors. Using NbN/Nb bilayers and individual pattering of both layers to form inductors allowed us to increase critical currents of the interlayer vias and minimize parasitic kinetic inductance associated with the vias and connections to JJs. Fabrication details and results of electrical characterization of NbN films, wires, and vias, and comparison with Nb properties are given.