30.3 A 512Gb 3b/Cell 7<sup>th</sup> -Generation 3D-NAND Flash Memory with 184MB/s Write Throughput and 2.0Gb/s Interface
Ji-Ho Cho, Dongku Kang, Jongyeol Park, Sang-Wan Nam, Jung-Ho Song, Bong-Kil Jung, Jae-Doeg Lyu, Hogil Lee, Won-Tae Kim, Hongsoo Jeon, Sung‐Hoon Kim, In-Mo Kim, Jae-Ick Son, Kyoungtae Kang, Sang-Won Shim, Jongchul Park, Eungsuk Lee, Kyung-Min Kang, Sang‐Won Park, Jaeyun Lee, Seung Hyun Moon, Pansuk Kwak, Byunghoon Jeong, Cheon An Lee, Ki-Sung Kim, Junyoung Ko, Taehong Kwon, Jun-Ha Lee, Yohan Lee, Chaehoon Kim, Myeong-Woo Lee, Jeong-yun Yun, HoJun Lee, Yonghyuk Choi, S. Hong Songcheol Hong, Jonghoon Park, Yoonsung Shin, Hojoon Kim, Hansol Kim, Chi-Weon Yoon, Dae Seok Byeon, Seungjae Lee, Jin-Yub Lee, Jaihyuk Song
Abstract
The exponential data size growth in high-speed networks is a key motivator for nonvolatile memory development. To support this demand, higher density NAND is required: with a smaller cell size and higher interface speed. Generally, scaling down NAND technology requires addressing several common issues: 1) As the number of WL stack layers increases, the cell-string current is reduced due to the increased resistance in a cell string, 2) Deterioration of cell-to-cell interference, due to the reduction of cell pitch, 3) Support of higher IO bandwidth for faster data transfer speed [1]. Another challenge of this work was to minimize the die size because the peripheral circuit area is comparable to that of the cell array. Hence, we integrated the peripheral circuits below the cell array as introduced in [2]. Also, to cope with lower metal-contact height, a novel structure for the capacitor device was used to maximize capacitance per unit area.