Inter-Layer Dielectric Engineering for Monolithic Stacking 4F2-2 T0C DRAM with Channel-All-Around (CAA) IGZO FET to Achieve Good Reliability (>104 s Bias Stress, >1012 Cycles Endurance)

Chuanke Chen, Xinlv Duan, Guanhua Yang, Congyan Lu, Di Geng, Ling Li, Ming Liu

20222022 International Electron Devices Meeting (IEDM)37 citationsDOI

Abstract

To address the stacking requirement of $4F^{2}-2$ T0C DRAM with vertical channel-all-around (CAA) IGZO FETs, for the first time, the effect of inter-layer dielectric (ILD) on CAA-IGZO FETs has been studied by varying dielectric material and process. By using optimized ILD and IGZO deposition cycle ratio, CAA-IGZO FET with high reliability is obtained. The optimized device exhibits a ${V}_{th}$ shift of less than 25 mV after $10^{4}s$ bias stress and no significant degradation after 10 12 cycles endurance. Our results provide an important reference for facilitating the monolithic stacking of multilayer IGZO FETs to realize 3D DRAM.

Topics & Concepts

DramStackingDielectricMaterials scienceReliability (semiconductor)OptoelectronicsLayer (electronics)Gate dielectricRandom access memoryElectrical engineeringNanotechnologyComputer sciencePhysicsVoltageTransistorNuclear magnetic resonanceComputer hardwareEngineeringQuantum mechanicsPower (physics)Semiconductor materials and devicesAdvancements in Semiconductor Devices and Circuit DesignThin-Film Transistor Technologies

Inter-Layer Dielectric Engineering for Monolithic Stacking 4F<sup>2</sup>-2 T0C DRAM with Channel-All-Around (CAA) IGZO FET to Achieve Good Reliability (&gt;10<sup>4</sup> s Bias Stress, &gt;10<sup>12</sup> Cycles Endurance)

Abstract

Topics & Concepts

Inter-Layer Dielectric Engineering for Monolithic Stacking 4F<sup>2</sup>-2 T0C DRAM with Channel-All-Around (CAA) IGZO FET to Achieve Good Reliability (>10<sup>4</sup> s Bias Stress, >10<sup>12</sup> Cycles Endurance)