Stacked Lateral Gate-All-Around Metal–Oxide–Semiconductor Field-Effect Transistors and Their Three-Dimensional Integrated Circuits
Shujun Ye, Liwei Liu, Yuanxiao Ma, Yeliang Wang
Abstract
Abstract According to the International Roadmap for Devices and Systems , gate-all-around (GAA, also known as a surrounding gate) metal–oxide–semiconductor field-effect transistor (MOSFET) will be the main device in integrated circuits (ICs). Lateral GAA (LGAA) MOSFETs have been applied in CMOS logic circuits from a 3-nm technology node. However, further shrinkage of the contacted gate pitch is difficult owing to the physics and processing limitations. Three-dimensional (3D) stacking of chips or wafers is therefore widely studied for high integration. However, the device distance between stacked chips or wafers is rarely less than 10 µm, which is too long considering the electrical resistance and transfer delay, especially for logic circuits. Complementary field-effect transistors are currently a widely used 3D logic device; however, a compatible process is required for the heterostructures. The authors previously developed a fabrication process for symmetric-source/drain vertical GAA (referred to as ultimate VGAA, UVGAA) MOSFET for the first time; a novel architectural 3D IC with stacking UVGAA-based devices (CMOS and/or SRAM) in the vertical direction was also developed. In this perspective, a fabrication process for stacked LGAA (SLGAA) MOSFETs in the vertical direction is proposed for the first time and a high integration 3D logic IC based on SLGAA MOSFETs is also developed. These novel 3D architectures lay the foundations for next-generation ICs.