CLIP: Load Criticality based Data Prefetching for Bandwidth-constrained Many-core Systems
Biswabandan Panda
Abstract
Hardware prefetching is a latency-hiding technique that hides the costly off-chip DRAM accesses. However, state-of-the-art prefetchers fail to deliver performance improvement in the case of many-core systems with constrained DRAM bandwidth. For SPEC CPU2017 homogeneous workloads, the state-of-the-art Berti L1 prefetcher, on a 64-core system with four and eight DRAM channels, incurs performance slowdowns of 24% and 16%, respectively. However, Berti improves performance by 35% if we use an unrealistic configuration of 64 DRAM channels for a 64-core system (one DRAM channel per core).
Topics & Concepts
DramComputer scienceEmbedded systemBandwidth (computing)Parallel computingMulti-core processorComputer architectureComputer hardwareComputer networkParallel Computing and Optimization TechniquesAdvanced Data Storage TechnologiesInterconnection Networks and Systems