8.4 A 116Gb/s DSP-Based Wireline Transceiver in 7nm CMOS Achieving 6pJ/b at 45dB Loss in PAM-4/Duo-PAM-4 and 52dB in PAM-2
Marc-Andre LaCroix, Euhan Chong, Weilun Shen, Ehud Nir, F. A. S. Musa, Haitao Mei, Mohammad-Mahdi Mohsenpour, Semyon Lebedev, Babak Zamanlooy, Carlos Carvalho, Xin Qian, Dmitry A. Petrov, Henry Wong, H. Ho, Yang Xu, Sina Naderi Shahi, Peter Krotnev, Chris Feist, Howard Huang, Davide Tonietto
Abstract
DSP-based transceivers above 100Gb/s have demonstrated the ability to handle up to 38dB insertion loss (IL) with low-to-moderate crosstalk [1-2]. At same time, power scaling techniques [3] have closed the energy efficiency gap compared with analog/mixed-signal transceivers on shorter links. Notwithstanding advances in materials and connectors, in large repeater-less backplanes, transceivers are required to operate reliably at 100Gb/s with more than 40dB IL. Furthermore, next generation computing and AI applications require 50Gb/s rates per lane on channels with more than 45dB loss but without the latency of forward error correction (FEC). In this paper we demonstrate a reconfigurable ADC-DSP SerDes capable of operating with BER ≤1E-05 at 112Gb/s in PAM-4 or Duo-PAM-4 across a 45dB loss channel, and 58Gb/s PAM-2 at <; 1E-15 over a 52dB loss channel without FEC, while achieving a power efficiency better than 6pJ/b. The SerDes architecture is shown in Fig. 8.4.1 and features extensive power scaling capability.