Backside Power Delivery With Relaxed Overlay for Backside Patterning Using Extreme Wafer Thinning and Molybdenum-Filled Slit Nano Through Silicon Vias
Peng Zhao, Liesbeth Witters, Anne Jourdain, Michele Stucchi, N. Jourdan, Jan Willem Maes, H. Bana, C. Zhu, Rami Chukka, Farid Sebaai, K. Vandersmissen, N. Heylen, D. Montero, S. Wang, K. D’havé, Filip Schleicher, Joeri De Vos, Gerald Beyer, Andy Miller, Eric Beyne
Abstract
Backside power delivery network (BSPDN) has gained much attention due to its potential to independently optimize signal and power routing. In this work, long slit nano through silicon vias (nTSVs) is used for high-density connections between frontside (FS)-patterned buried power rails (BPRs) and orthogonally patterned metal rails on the wafer backside (BS). These nTSVs are in situ patterned on top of BPR with self-alignment using FS lithography, and the length of the slits can also be tuned. This design relaxes overlay requirements for BS patterning that are typically stringent due to wafer grid distortions during bonding. Additionally, extreme wafer thinning stopping on a 10 nm Si0.75Ge0.25 etch stop layer (ESL) is enabled using an optimized thinning sequence with excellent total thickness variation (TTV) control. For the first time, low resistance barrier-free Molybdenum (Mo)-filled nTSVs are demonstrated, confirming the potential for further scaling compared to TiN/W-filled counterparts.