Unveiling the Influence of Channel Thickness on PBTI and LFN in Sub-10 nm-thick IGZO FETs: A Holistic Perspective for Advancing Oxide Semiconductor Devices
Gan Liu, Qiwen Kong, Xiaolin Wang, Yi-Hsin Tu, Zijie Zheng, Chen Sun, Dong Zhang, Yuye Kang, Kaizhen Han, Gengchiau Liang, Xiao Gong
Abstract
In this work, we present the first systematic and comprehensive investigation into the impact of channel thickness (t <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CH</inf> ) on the positive bias temperature instability (PBTI) and low frequency noise (LFN) of Indium-Gallium-Zinc-oxide (IGZO) FETs with sub-10 nm t <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CH</inf> . A novel Noise-PBTI-Noise (NPN) measuring scheme was proposed that combines LFN and PBTI measurements at different temperatures (T). Our study yields several key findings of significance: (1) FETs with a thinner t <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CH</inf> exhibit a higher susceptibility to electron trapping effects while demonstrating greater resilience to the hydrogen (H) effect. (2) Smaller t <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CH</inf> values are associated with higher levels of LFN. (3) The mobility fluctuation model (Δµ) effectively describes the LFN characteristics of the FETs, regardless of t <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CH</inf> values. Notably, we achieved the record low Hooge's parameter (α <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">H</inf> ) of 2.46×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-4</sup> among all amorphous oxide channel transistors. (4) The passivation effect of the H component formed during PBTI on existing traps was identified for the first time. This work highlights the significance of adopting a holistic approach to understanding and optimizing device performance in advancing oxide semiconductor device technology.