A 4.4-mW 19–46-GHz Low-Noise Amplifier with Pole-Converging Gain Flattening and Triple-Resonance Input Matching
Jiahan Fu, C.S. Song, Yihui Wang, Liang Wu
Abstract
A cascode low-noise amplifier (LNA) features wide frequency bandwidth with low power consumption. At the cascode stage, a pole-converging gain flattening technique is employed, simultaneously extending its −3-dB bandwidth and flattening the gain response across the entire frequency range. To substantially expand the frequency bandwidth of the input matching, a transformer-based triple-resonance network is proposed. In addition, the current reuse embedded helps reduce the DC power consumption. Prototyped in a 40-nm CMOS process, the proposed LNA measures a frequency range from 19 to 46 GHz, gain of 12.4 dB with 1.76-dB ripple, noise figure (NF) between 3.4 and 4.6 dB, and IP<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</inf> from −15 to −19.4 dBm. It consumes only 4.4-mW power from a 1-V supply, resulting in a figure of merit (FoM) of 21.6. The core area occupied is 0.096 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>.