A highly reliable 1.8 V 1 Mb Hf<sub>0.5</sub>Zr<sub>0.5</sub>O<sub>2</sub>-based 1T1C FeRAM Array with 3-D Capacitors
Jun Okuno, Takafumi Kunihiro, Tsubasa Yonai, Ryo Ono, Yusuke Shuto, Ruben Alcala, Maximilian Lederer, Konrad Seidel, Thomas Mikolajick, Uwe Schroeder, Masanori Tsukamoto, Taku Umebayashi
Abstract
This study proposes a novel 1 Mb one-transistor one-capacitor ferroelectric random access memory array based on ferroelectric Hf <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</inf> Zr <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</inf> O <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> with 3D cylindrical capacitors. We obtain a perfect functionality with a sufficient memory window at a small projected cylinder area of 0.028 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> at an operating voltage of 1.8 V by reducing the C <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BL</inf> and optimizing the structure of the capacitors. We achieve a cycling endurance of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sup> cycles and 1-month retention at 85°C. The reliability is further improved to over 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sup> cycles and 10 years at 85°C retention if the operating voltage is increased to 2.4 V. This technology matches the requirements of last-level cache and low-power systems in chips for Internet of Things applications.