Parasitic Inductances Extraction for SiC Power Modules Using An Enhanced Two-Port S-Parameter Approach
Zhongjing Wang, Zhao Yuan, Yue Zhao
Abstract
Parasitic inductance of power modules is one nonnegligible part of inductance on converters’ current commutation loop (CCL). Larger CCL inductance leads to higher switching oscillation, voltage overshoot, electromagnetic interference (EMI), and larger power losses. This paper uses two-port scattering (S) parameter measurement to extract the parasitic inductance of the power module. The innovation of this paper is that it considered the impact of mutual inductance and fixture printed circuit board (PCB) when using S-parameter approach. Accurate internal parasitic inductance values can be obtained by logic analysis, no matter used in a traditional two-level (2-L) inverter or three-level (3-L) T-type inverter. And it provides the guidance to build the fixture PCB board to connecting vector network analyzer (VNA) and the module, which has not been discussed in the existing literature. The approach is experimentally validated by a commercial 1200V SiC half-bridge power module.