2.3 Emerald Rapids: 5th-Generation Intel<sup>®</sup> Xeon<sup>®</sup> Scalable Processors
Ashley O. Munch, Nevine Nassif, Carleton L. Molnar, Jason Crop, R. Gammack, Chinmay P. Joshi, Goran Zelic, Kambiz Munshi, Min Huang, Charles R. Morganti, Sireesha Kandula, Arijit Biswas
Abstract
The 5 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sup> -Generation Intel Xeon Scalable Processors (codenamed Emerald Rapids) support up to 64 cores, greater than 300MB shared L3 cache, 8 DDR5 channels at 5600MT/s with 1DPC, 32GT/s PCIe/CXL lanes, 20GT/s UPI lanes composed of 2 die (Fig. 2.3.1) in a multichip package. This generation delivers an 18% performance improvement for general integer compute workloads and a 24% improvement for floating-point workloads at iso power vs. the 4 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sup> -Gen Xeon processors [1]. This is achieved through an improved core, enhanced process technology, increased core count, significantly larger cache, higher DDR memory speeds, die reductions, and power efficiency improvements at idle conditions. Manufacturing is on the Intel 7 process technology optimized for server usage with improved transistor speed and a focus on leakage and dynamic capacitance reduction enabling +3% frequency/W enhancements over the prior generation process revision. The key power-efficiency improvements at idle were achieved through improvements to the fully integrated voltage regulators (FIVR) [2, 3] to decrease the regulator losses at lower utilization, enhanced active idle detection and power savings, and package C6 power reduction.