First Demonstration of 4-Layer Stacked Planar Channel-All-Around (P-CAA) IGZO FETs with Cost-Effective Process for High-Density 1T1C 3D DRAM
Xuezheng Ai, Weiwei Li, Chen Gu, Chuanke Chen, Xinlv Duan, Congyan Lu, Jianqi Chen, Xiangsheng Wang, Kaiping Zhang, Jin Dai, Mingxu Liu, Jiebin Niu, Chuanhui Huang, Jinjuan Xiang, Yong Yu, Feng Shao, Guanhua Yang, Yu Liu, Xiaomeng Liu, Shaohua Wang, Bok-Moon Kang, Gengfei Li, Shenjie Zhao, Nianduan Lu, Di Geng, Guilei Wang, Chao Zhao, Ling Li, Ming Liu
Abstract
We demonstrated the first 4-layer stacked planar channel-all-around (P-CAA) IGZO FETs for cost-effective and high-density 3D DRAM, which addresses the scaling limitation encountered by planar 2D device. This innovative architecture involves a sequential deposition of all planar layers in the cell array. Then, a cost-effective fabrication process is carefully designed to manufacture transistors on all layers. The proposed approach tackles the problem of low fabrication efficiency encountered by the conventional layer by layer stacked 3D DRAM. Leveraging the remarkably low leakage current of the IGZO FETs, the P-CAA IGZO FETs based bit cell can have long data retention time. These exceptional properties position it as a competitive candidate for emerging low-cost and high-density monolithic 3D DRAM.