Experimental demonstration, challenges, and prospects of the vertical SiC FinFET
Florin Udrea, K. Naydenov, Hyemin Kang, Tomohisa Kato, Eiji Kagoshima, Hiromu Fujioka, H. Tomita, Takeshi Nishiwaki, Hiroshi Fujiwara, Tsunenobu Kimoto
Abstract
In this paper we report the first vertical, normally-off high voltage SiC FinFET. The device has a breakdown voltage of ~ 1kV, a specific on-state resistance R <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</inf> of 0.7mΩcm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and a threshold voltage V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</inf> of 2.2V. It is based on a trench technology with a pitch between trenches (fin width W <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fin</inf> ) of 144nm. The FinFET effect is discussed for this specific device and for a wider class of SiC power devices rated at different voltages. A calibrated TCAD model is developed for a physical insight into the device’s operation. Finally, the paper outlines the challenges and prospects of this structure.