An 11.1-to-14.9GHz Digital-Integral Hybrid-Proportional Fractional-N PLL with an LC DTC Achieving 0.52μs Locking Time and 41.3fs Jitter
Hongzhuo Liu, Wei Deng, Haikun Jia, Baoyong Chi
Abstract
With the abundance of mm-wave bands and a drastically increased number of devices, new generations of wireless communication and cognitive radio call for better agility and quality of frequency synthesizers. The bang-bang digital PLLs (BBPLL) become popular for its omission of the bulky analog loop filter and the flexibility to implement bandwidth gear shifting (BWGS), and some of the fast-lock and low-jitter BBPLLs have been reported [1]–[3]. However, the nonlinearity of the bang-bang phase detectors (BBPD) caused quantization noise, which degrades the phase noise (PN) performance. The analog PLLs [4], [5], on the contrary, have linear components and well-defined loop parameters, but suffer the inability of fast locking. Moreover, most of the existing fast-lock BBPLLs are based on PLL's integrator and the logics adjust the tuning word incrementally, which caused a long time for wideband hopping. The adaptive frequency switching [1] has the ability to predict the tuning word in a short time by estimating the DCO tuning gain, but it relies on the linearity of the code-frequency curve of the DCO.