Characterization of Time Delay in Power Hardware in the Loop Setups
Efrén Guilló-Sansano, Mazheruddin Syed, Andrew Roscoe, Graeme Burt, Federico Coffele
Abstract
The testing of complex power components by means of power hardware in the loop (PHIL) requires accurate and stable PHIL platforms. The total time delay typically present within these platforms is commonly acknowledged to be an important factor to be considered due to its impact on accuracy and stability. However, a thorough assessment of the total loop delay in PHIL platforms has not been performed in the literature. Therefore, time delay is typically accounted for as a constant parameter. However, with the detailed analysis of the total loop delay performed in this article, variability in time delay has been detected as a result of the interaction between discrete components. Furthermore, a time delay characterization methodology (which includes variability in time delay) has been proposed. This will allow for performing stability analysis with higher precision as well as to perform accurate compensation of these delays. The implications on stability and accuracy that the time delay variability can introduce in PHIL simulations has also been studied. Finally, with an experimental validation procedure, the presence of the variability and the effectiveness of the proposed characterization approach have been demonstrated.