Novel Reconfigurable Field-Effect Transistor With Asymmetric Spacer Engineering at Drain Side
Yan Yao, Yabin Sun, Xiaojin Li, Yanling Shi, Ziyu Liu
Abstract
In this article, a novel reconfigurable field-effect transistor with an asymmetric underlap channel extension at drain side (UCED-RFET) is proposed for the first time. The influence of underlap extension is investigated by extensive 3-D device simulation. Results show that compared to the conventional RFET with symmetrical underlap-channel extension at source and drain end, the ON-state saturated current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> ) of our proposed UCED-RFET is greatly increased without degenerating the OFF-state leakage current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ), and the ratio of I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> is up to 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">9</sup> . The underlying physical mechanism is explored and the enhanced gate coupling is demonstrated to contribute to the improved performance in our proposed UCED-RFET. Moreover, the effects of gate dielectric materials and different spacers are investigated, and the results correlated with the scaling properties are also reported.