Exploring the high-throughput and low-delay hardware design of SM4 on FPGA
Yixiao Chen, Jinfeng Song, Shuai Chen, Yuan Cao, Jing Ye, Huawei Li, Xiaowei Li, Xin Lou, Enyi Yao
Abstract
SM4 (or SMS4) is a 32-round unbalanced Feistel block cipher. This paper explores the hardware design method of SM4 for different scenarios on FPGA. Targeting the real-time high speed communication system on FPGA, we construct the pipeline across the unrolled rounds to gain balanced pipeline stages with online and offline key expansion schemeS. Meanwhile, for the low-delay application scenario, various SM4 structures are implemented to show the trade-off relationship between the number of unrolled rounds and the performance metrics. The experimental results show that in the high-throughput application scenario, our optimization method can achieve a throughput of 118. <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$19\text{Gbps}$</tex> with relatively higher efficiency <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\text{Mbps}/\text{area})$</tex> ; in the low-delay application scenario, the delay <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\times$</tex> area can be minimized to 177.18 ns <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\times(\text{FF}+ \text{LUT})$</tex> when unfolding 2 rounds of operations.