Litcius/Paper detail

A CNN-Based CMP Planarization Model Considering LDE Effect

Han Bao, Lan Chen

2020IEEE Transactions on Components Packaging and Manufacturing Technology20 citationsDOI

Abstract

As integrated circuit (IC) industry advances to the nanometer scale, layout pattern plays more and more important role on chip fabrication. Layout-dependent effect (LDE) studies how different patterns influence the fabrication results. Chemical–mechanical polishing (CMP), one of the most important processes during IC fabrication, is strongly influenced by LDE. The purpose of this article is to show a convolutional neural network (CNN)-based method to model post-CMP surface topography problem. The method accurately predicts the topological height of the chip surface after CMP by using CNN to abstract features from layout patterns, aiming to analyze defects that may cause failure. This article first addresses about the principles and practicability of using the CNN method to build a CMP model, then builds up a complete CNN structure, and compares the CNN-based model with a traditional pressure-distribution-based CMP model. We designed test chips containing different structures and fabricated them with 28- and 45-nm process nodes. Surface topography is measured using atomic force profiler (AFP) and scanning electron microscope (SEM). The result shows that the total root-mean-squared error (RMSE) of the CNN-based model is 22.41 A, whereas the RMSE of the pressure-distribution-based model is 65.54 A. The CNN-based CMP model shows better accuracy.

Topics & Concepts

Chemical-mechanical planarizationMean squared errorConvolutional neural networkChipFabricationIntegrated circuitComputer sciencePolishingScanning electron microscopeSurface (topology)Process (computing)Materials scienceArtificial intelligencePattern recognition (psychology)AlgorithmMathematicsOptoelectronicsComposite materialGeometryTelecommunicationsStatisticsOperating systemPathologyAlternative medicineMedicineAdvanced Surface Polishing TechniquesIntegrated Circuits and Semiconductor Failure AnalysisAdvanced machining processes and optimization