Back-End-of-Line-Compatible Scaled InGaZnO Transistors by Atomic Layer Deposition
Jie Zhang, Zehao Lin, Zhuocheng Zhang, Ke Xu, Hongyi Dou, Bo Yang, Adam Charnas, Dongqi Zheng, X. Zhang, Haiyan Wang, Peide D. Ye
Abstract
In this work, we report on back-end-of-line (BEOL)-compatible InGaZnO indium gallium zinc oxide (IGZO) thin film transistors (TFTs) with extreme scaled device dimension including channel thickness ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${T}_{\text {ch}}{)}$ </tex-math></inline-formula> down to 1.5 nm and channel length ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${L}_{\text {ch}}{)}$ </tex-math></inline-formula> down to 60 nm. These IGZO channels with a high In atomic ratio of 92% were derived by atomic-layer-deposition (ALD), where the IGZO thickness could be precisely controlled by ALD cycles. These TFTs were subjected to a mild O2 annealing at 250 °C, the effect of which is also systematically investigated. It is found that both <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${T}_{\text {ch}}$ </tex-math></inline-formula> and O2 annealing have significant effects on TFT performance. By using optimized O2 annealing conditions, the ALD IGZO TFTs with scaled <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${T}_{\text {ch}}$ </tex-math></inline-formula> of 1.5 nm and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${L}_{\text {ch}}$ </tex-math></inline-formula> of 60 nm exhibit desirable electrical performance including a high ON/ OFF ratio ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}{)}~\sim ~10^{{11}}$ </tex-math></inline-formula> , a decent high Ion of 354 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{A}/\mu \text{m}$ </tex-math></inline-formula> under <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {DS}}$ </tex-math></inline-formula> of 1.2 V, a steep subthreshold swing (SS) of 68 mV/dec, a small drain-induced-barrier-lowering (DIBL) of 30 mV/V, and a normal-off operation, which is comparable to the state-of-art sputtered IGZO TFTs. Furthermore, the optimized TFTs also exhibit significantly resolved threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {T}}{)}$ </tex-math></inline-formula> roll-off and a remarkably high degree of stability to the positive gate bias stress (PBS). A trap model with its possible microscopic origin is proposed, which explains well the dependence of electrical performance on both <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${T}_{\text {ch}}$ </tex-math></inline-formula> and O2 annealing, thus providing a new insight into the reliability of IGZO TFTs.