A 78-mW 220-GHz Power Amplifier With Peak 18.4% PAE in 250-nm InP HBT Technology
Amirreza Alizadeh, Petra Rowell, Zach Griffith, Miguel Urteaga, M.J.W. Rodwell
Abstract
We report a three-stage power amplifier (PA), using 250-nm indium phosphide (InP) heterojunction bipolar transistors (HBTs), that achieves 18.4% peak power-added efficiency (PAE) with 18.8-dBm associated output power ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_\text{out}$</tex-math> </inline-formula> ) and 13.8-dB associated power gain at 221.5 GHz. The amplifier has 19.5-dB peak <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$S_\text{21}$</tex-math> </inline-formula> and 212–238-GHz 3-dB bandwidth. The output stage combines the output power of four power transistor cells, each cell being a capacitively degenerated common-base stage with four parallel HBTs, each HBT having 5- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu\text{m}$</tex-math> </inline-formula> emitter length. Within each power transistor cell, separate base dc bias resistances for each emitter finger significantly increase the safe operation area (SOA), allowing dc bias at a greater collector current density at any given collector–emitter voltage. The increased SOA improves the amplifier <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_\text{out}$</tex-math> </inline-formula> and power-added efficiency (PAE). The simulated loss of the 4:1 output power combiner is only 1 dB at 230 GHz. To the authors’ knowledge, this is the highest published PAE for a transistor amplifier operating above 200 GHz.