Design of Full Adder and Parity Generator Based on Reversible Logic
Sunakshi Sharma, Vijay Kumar Sharma
Abstract
For electronic circuits, one of the most promising technology in modern days is Quantum Cellular Automata (QCA). It provides high speed, low power consumption and higher density as compared to CMOS technology. Quantumdot cell is a basic device which can be used to implement logic gates and various other digital circuits. In QCA, reversible computing approach helps in mitigating the power dissipation, hence providing a reliable solution. This paper presents a novel design for a reversible circuit which act as full adder, even parity as well as odd parity generator. Our proposed design is simple in structure with no garbage output. The design consists minimum number of clock zones and can be used for implementing various other logic gates. Simulation results are verified using software QCADesigner2.0.3.