Evaluation of Single-Event-Transient Effects in Reconfigurable Field Effect Transistor Beyond 3 nm Technology Node
Yabin Sun, Jingyan Shao, Ziyu Liu, Xiaojin Li, Yun Liu, Yanling Shi
Abstract
In this article, the single-event-transient (SET) in reconfigurable field-effect transistor (RFET) is evaluated by 3-D technology computer-aided design (TCAD) simulation for the first time. The effects of linear energy transfer (LET) values, electrical bias, strike location, and angle are investigated in detail. For heavy ion with LET of 10 MeV <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\cdot $ </tex-math></inline-formula> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /mg and characteristic radius of 1 nm, the peak value of drain SET current is up to 0.237 mA for n-type program, which is much higher than the saturated conduction current of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.22~\mu \text{A}/\mu \text{m}$ </tex-math></inline-formula> . The peak SET current increases from 0.18 to 0.36 mA as <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {DS}}$ </tex-math></inline-formula> ranges from 0.8 to 1.4 V. The drain voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {DS}}$ </tex-math></inline-formula> ) has a great impact on SET response and a higher lateral electric field will worsen the SET effects. The most sensitive position is confirmed to be not only related to the electric field distribution, but also the distance away from drain terminal. A serious SET effect is observed with a smaller angle. Furthermore, the impact of SET effect on NAND2/NOR2 multifunctional logic gates circuit based on RFETs is also evaluated. When striking the end of the changing edge of the input signal, the rise and fall relative propagation delays of NAND2 logic gates circuit are up to 34.49% and 35.04% respectively, with LET of 6 MeV <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\cdot $ </tex-math></inline-formula> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /mg. This work provides guidelines for RFET radiation-hardened technology in future extreme environment electronics applications.