Analysis of varied architectural configuration for 7T SRAM bit cell
Bhawna Rawat, Poornima Mittal
Abstract
In this paper three different bitline configuration of 7T SRAM bit cell – 7TDE, 7TSE and 7THE - are designed for 32 nm technology node and the simulation results are analyzed. The static noise margin obtained for 7TDE, 7TSE and 7THE for hold operation are - 75, 75 and 87 mV respectively, while for the read operation are 30, 75 and 87 mV respectively. The bit cell is a part of a larger circuit and embedded circuits are subjected to temperature variation during its course of operation. So the bit cell are analyzed for temperature variation from 25 ⁰C to 110 ⁰C. This analysis highlights that the 7THE bit cell has higher temperature tolerance for read and hold operation whereas the 7TSE has a better write operation temperature tolerance. While 7TDE shows inferior performance for all operation modes.