A 16.3 dBm 14.1% PAE 28-dB Gain $W$ -Band Power Amplifier With Inductive Feedback in 65-nm CMOS
Van‐Son Trinh, Jung‐Dong Park
Abstract
We present a W-band four-stage power amplifier (PA) in a 65-nm CMOS using a push-pull configuration with inductive feedback neutralization which achieves the highest figure of merit (FOM) compared to the recently reported CMOS PAs. The device was gradually tapered from the output to the input stage to optimize the power-added efficiency (PAE) while achieving high power gain with compact impedance matching with a transformer (TF). Interstage conjugate matching was also carried out with a TF to design a compact high-gain PA. Working under a supply voltage of 1.2 V, the proposed PA achieves a power gain of 28.2 dB with the 3-dB gain bandwidth of 7 GHz (76.8-83.8 GHz), a saturated output power of 16.3 dBm, and a peak PAE of 14.1% at 81.6 GHz with power dissipation of 234 mW. The total chip size is 0.714 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and the core size excluding pads is only 0.121 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .