GNRFET and RRAM Based Digital Gates in Ternary Logic
Shaik Javid Basha, P. Venkatramana
Abstract
The designs of ternary logic circuits are proposed in this work. The ternary logics are considered as best technology than binary as it provides high-speed, low occupying area and low wire count, respectively. An efficient method is presented to develop the ternary gates utilizing furistic device technologies such as graphene nanoribbon field effect transistors (GNRFETs) and resistive random-access memory (RRAM). GNRFETs are a noteworthy substitute for the traditional complementary metal oxide semiconductors (CMOS) because it exhibits good electrical, thermal and mechanical properties. The standard ternary inverter (STI), AND, NAND, OR and NOR schematics are developed. The industry standard Synopsys based Hewlett-simulation program with integrated circuit emphasis (HSPICE) tool is utilized to analyze transient waveforms. The delay, power and PDP of the proposed designs are investigated and compared to existing design technologies. From the analysis, it is observed that presented deigns enhanced the total performance by 56% than the existing circuits.